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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI

10.1109/TPEL.2015.2476356, IEEE Transactions on Power Electronics

EMC-aware Design of a Planar Inductor for

Low-proﬁle OLED Drivers

Jurica Kundrata, Adrijan Baric

University of Zagreb, Faculty of Electrical Engineering and Computing

Unska 3, 10000 Zagreb, Croatia

E-mail: jurica.kundrata@fer.hr, adrijan.baric@fer.hr

Abstract—This paper presents the design of a planar inductor

used in a low-proﬁle OLED driver for large-area lighting. The

design takes into account both the buck converter requirements

and the electromagnetic compatibility issues. Multiple inductor

design cases are investigated using EM simulations and veriﬁed

by measurements. The properties of the planar inductors are

represented by its magnetic moment and the modiﬁed quality

factor which also includes the power losses inherent to the

buck converter. The multi-objective optimization shows that the

designs which simultaneously maximize the quality factor and

minimize the magnetic moment of the planar inductor are located

along the resonant frequency limit. The result of the optimization

process is the inductor design which introduces minimum power

losses in the buck converter for a given level of radiated emissions.

Index Terms—planar inductor, electromagnetic modelling,

electromagnetic compatibility, multiobjective optimal design, de-

sign of experiments

I. INTRODUCTION

The organic light-emitting diode (OLED) lighting is an

emerging ﬁeld of the organic, large area electronics research

area [1]. These luminaries are based on OLED cells which

are surface, diffuse light sources. The OLED luminaries are

commonly realized on a glass substrate, but OLED cells based

on a ﬂexible foil are the current state-of-the-art [2].

Integrating the OLED cell with the driver electronics in a

modular luminary will reduce the luminary cost. The planar

nature of the cell implies a low proﬁle realization of the

luminary. The OLED driver and its components are embedded

in the backplane and connected to the OLED cell forming a

complete lighting device, i.e. an OLED module. The OLED

module can be used in a large-area luminary, e.g. wall lighting

which consists of dozens of tiled modules.

The function of the driver is to regulate the current supplied

to the OLED cell. An example of a low-proﬁle driver designed

for an OLED luminary is described in [3]. The OLED driver

is based on a switching-mode power supply that uses the buck

converter topology. An external inductor is embedded in the

backplane to preserve the low proﬁle of the OLED module.

Due to the low-proﬁle requirements and the proximity of the

OLED cell, the planar inductor exhibits a number of parasitic

This work was supported by the European Commision under the Seventh

Framework Programme (FP7) through project IMOLA Intelligent light man-

agement for OLED on foil applications (Grant Agreement No. 288377).

effects which have a great impact on the efﬁciency of the buck

converter. The design parameters of the planar inductor have

to be optimized in order to minimize the power losses.

The planar inductors commonly consist of a number of

turns and each turn acts as a loop antenna [4]. Increasing the

operating frequency of a low-proﬁle power converter allows

for its miniaturization. At the operating frequencies ≥ 1 MHz

the inductor can emit a considerable amount of radiation.

Furthermore, an OLED wall lighting consists of an array

of planar inductors and the total radiated emission is the

sum of the emissions of the tiled modules. Electromagnetic

compatibility (EMC) of the OLED modules then becomes a

critical topic.

Buck converters placed at the Point-of-Load (PoL) often

use a planar inductor due to limited space [5], [6]. The use

of embedded inductors in power converters is studied in [7]

where the design of a planar inductor is parametrized and

applied to a printed circuit board (PCB). In [8] a planar

inductor is optimized w.r.t. the power converter efﬁciency

and maximum power density while a similar study of the

multiobjective optimization of the planar inductor is done in

[9]. The power losses in the inductor due to the eddy currents

(proximity effect) is studied in [10]. The electromagnetic

compatibility of the power converters, i.e. the buck converters

is studied in [11] and [12] where the conducted emissions of

a buck converter are modelled in a wide frequency range. In

[13] the reduction of radiated emissions is considered w.r.t.

the PCB layout and in [14] the EMC considerations are a part

of a multiphysics constraint. In [15] an air-core solenoid used

in the buck converter is characterized w.r.t. the magnetic ﬁeld

emissions. The emergence of the low-proﬁle planar OLED

luminaries with applications in large-area lighting motivates

the research of such luminaries from the power converter and

EMC perspectives simultaneously.

This paper combines the optimization of the planar inductor

w.r.t. the buck converter requirements with the optimization

w.r.t. the EMC requirements. The goal of this co-optimization

is to design a planar inductor which has low radiated emissions

and introduces minimum power losses in the OLED driver. The

co-optimization forms a multiobjective optimization process

w.r.t. the geometrical design parameters of the planar inductor.

The OLED module, i.e. the planar inductor is characterized

using 3D EM simulations in Section II and the equivalent-

circuit model in Section III models the simulation results. A

modiﬁed quality factor is introduced in Section IV in order to

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用于低轮廓OLED驱动器的平面电感器的

EMC感知设计

尤里察·昆德拉塔，阿德里扬·巴里奇萨格勒布大学，电气工程

与计算学院克罗地亚萨格勒布乌恩斯卡3号，10000电子邮件：

jurica.kundrata@fer.hr,adrijan.baric@fer.hr

摘要—本文介绍了一种用于大面积照明的低轮廓OLED驱动

器中的平面电感器设计。该设计同时考虑了降压变换器的要求

和电磁兼容性问题。通过电磁仿真研究了多种平面电感器设计

方案，并通过测量进行了验证。平面电感器的特性由其磁矩和

改进的品质因数表示，后者还包含了降压变换器固有的功率损

耗。多目标优化结果表明，同时最大化品质因数并最小化平面

电感器磁矩的设计位于谐振频率极限附近。优化过程的结果是，

在给定辐射发射水平下，使降压变换器引入最小功率损耗的电

感器设计。

索引术语—平面电感器，电磁建模，电磁兼容性，多目标优

化设计，实验设计

I.引言

有机发光二极管（OLED）照明是有机大面积电子学

研究领域的一个新兴方向 [1]。这些灯具基于OLED单元，

属于面型漫射光源。OLED灯具通常在玻璃基板上实现，

但基于柔性箔的OLED单元是当前的先进技术 [2]。

将OLED单元与驱动电子器件集成在模块化灯具中，

可降低灯具成本。OLED单元的平面特性意味着灯具的低

轮廓实现。OLED驱动器及其组件嵌入背板中，并与

OLED单元连接，形成完整的照明装置，即OLED模块。

该OLED模块可用于大面积灯具，例如由数十个拼接模块

组成的壁灯。

驱动器的功能是调节供给OLED单元的供电电流。文

献 [3]中描述了一种为OLED灯具设计的低剖面驱动器示

例。该OLED驱动器基于采用降压转换器拓扑的开关模式

电源。为了保持OLED模块的低剖面特性，外部电感器被

集成在背板中。由于低剖面要求以及与OLED单元的近距

离，平面电感器表现出多种寄生特性

本工作由欧洲委员会第七框架计划（FP7）通过IMOLA项目“智能

照明在箔基OLED应用中的应用”（资助协议编号288377）资助。

对降压转换器的效率有重大影响。必须优化平面电感器的

设计参数，以最小化功率损耗。

平面电感器通常由若干匝组成，每一匝都相当于一个

环形天线 [4]。提高低剖面电源转换器的工作频率有助于

实现其小型化。在 ≥ 1 MHz的工作频率下，电感器可能

会发射大量辐射。此外，OLED壁灯由平面电感器阵列构

成，总辐射发射是各拼接模块辐射发射的总和。因此，

OLED模块的电磁兼容性（EMC）成为一个关键问题。

由于空间受限，放置在负载点（PoL）的降压转换器

通常使用平面电感器 [5], [6]。文献 [7]研究了电源变换器

中嵌入式电感器的应用，其中对平面电感器进行了参数化

设计并应用于印刷电路板（PCB）。在 [8] 中，针对电

源转换器效率和最大功率密度对平面电感器进行了优化，

而文献[9]则进行了类似的平面电感器多目标优化研究。文

献 [10]研究了由于涡流（邻近效应）引起的电感器中的功

率损耗。关于电源变换器（即降压转换器）的电磁兼容性，

文献 [11] 和 [12]在宽频率范围内对降压转换器的传导发

射进行了建模。文献[13] 从PCB布局角度考虑了辐射发射

的抑制，而文献 [14] 将电磁兼容性（EMC）考量作为多

物理场约束的一部分。文献 [15] 对降压转换器中使用的

空心螺线管的磁场发射特性进行了表征。低剖面平面

OLED灯具在大面积照明中的应用兴起，推动了从电源变

换器和电磁兼容性两个角度同时对该类灯具开展研究。

本文将平面电感器针对降压转换器要求的优化与针对

EMC要求的优化相结合。该协同优化的目标是设计一种

具有低辐射发射且在OLED驱动器中引入最小功率损耗的

平面电感器。该协同优化构成了针对平面电感器几何设计

参数的多目标优化过程。

OLED模块，即平面电感器，在第二节中通过3D电磁

仿真进行表征，第三节中的等效电路模型对仿真结果进行

了建模。在第四节中引入了改进的品质因数以

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Fig. 1. The OLED module consisting of the OLED cell and the backplane

which contains the OLED driver (the driver chip and the planar inductor),

and the layer stack-up of the planar inductor used in EM simulations.

reﬂect the power losses of the buck converter, while Section

V relates the radiated emissions of the planar inductor to

its magnetic moment. The modiﬁed quality factor and the

magnetic moment form the ﬁgures-of-merit (FoMs) consid-

ered in the multiobjective optimization. Section VI presents

the parametrized models of the FoMs. The co-optimization

described in Section VII explores the conditions and the

trade-offs present when simultaneously optimizing the buck

converter and EMC performance. The veriﬁcation of the

modelling results and co-optimization is presented in Section

VIII. The optimization and veriﬁcation results are discussed

in IX, while the conclusions are presented in Section X.

II. ELECTROMAGNETIC SIMULATIONS

The low-proﬁle OLED module is analysed using EM sim-

ulations. It consists of the OLED cell encapsulated in glass

(116 x 118 mm

) and the backplane that contains the driver

(Fig. 1). The concept of the device is described in [3].

The layer structure of the OLED module is shown in Fig.

1. The backplane has the same dimensions as the OLED cell.

The cathode of the OLED cell covers the bottom of the cell

and it is represented by the metal layer M0. The dielectric

layer D0 represents the glass encapsulation of the OLED cell

and the glue between the OLED cell and the backplane. The

backplane is made of a 250-µm thick FR4 substrate (layer

D1) with two 35 µm thick copper layers (M1 and M2). The

inductor is patterned on the metal layer M2. The metal layer

M1 is facing the OLED cell.

Fig. 2 shows the planar inductor design and its geometrical

parameters. The design parameters are the track width w, the

track spacing s, the ﬁll ratio R and the outer dimension D.

The ﬁll ratio R is the ratio of the number of turns of the

inductor N and the maximum number of turns N

max

for a

given geometry.

The dimensions of the planar inductor and its inductance

are constrained by the size of the OLED cell. As the planar

inductor is close to the OLED cathode, the proximity of the

planar inductor and cathode causes inductance degradation due

Fig. 2. The geometry of the planar inductor consisting of two subcoils with

its design parameters, the ports P0, P1 and P2 and the port structure with the

marked reference plane ∆-∆

(M1 - light gray and M2 - dark gray).

to the eddy currents and increased parasitic capacitance. The

planar inductor is realized on the M2 layer of the backplane,

i.e. the layer which is further away from the OLED cell

to reduce the parasite capacitance between the OLED and

planar inductor. The copper tracks that connect the inductor,

the driver and the OLED cell are realized in the metal layer

M1. The planar inductor consists of two subcoils which are

symmetric and wound in opposite directions. The subcoils will

produce opposite magnetic moments.

The planar inductor is deﬁned as a two-port structure. The

ports are deﬁned at the points P1 and P2 of the inductor layout

in Fig. 2. The ports are connected by vias to the the metal layer

M1.

The 3D EM simulations of the OLED module are done

in order to model the electrical characteristics of the planar

inductor w.r.t. its design parameters. The RF module of the

software package COMSOL Multiphysics [16] is used to

simulate the S-parameters of the inductor structure.

The frequency range of interest is from 300 kHz to 300

MHz. The lower frequency limit is set approximately a decade

below the operating frequency of the buck converter, while the

upper frequency limit is set to include the resonant behaviour

of the analysed inductor.

III. EQUIVALENT-CIRCUIT MODELLING

Fig. 3 shows the electrical schematic of the system consid-

ered in this paper, i.e. the output stage of the buck converter,

planar inductor and OLED cell.

The output stage of the buck converter consists of the

switching pDMOS transistor T

and freewheeling diode D

The transistor T

is characterized by its on-resistance R

DS,ON

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图1.由OLED单元和背板（包含OLED驱动器（驱动芯片和平面电感器））

组成的OLED模块，以及用于电磁仿真中的平面电感器的层叠结构。

反映降压转换器的功率损耗，而第五节将平面电感器的辐

射发射与其磁矩相关联。改进的品质因数和磁矩构成了多

目标优化中考虑的性能指标（FoMs）。第六节介绍了这

些性能指标的参数化模型。第七节描述的协同优化探讨了

在同时优化降压转换器和EMC性能时存在的条件和权衡。

第八节展示了对建模结果和协同优化的验证。第九节讨论

了优化与验证结果，而结论部分在第十节中给出。

二、电磁仿真

使用电磁仿真分析了低轮廓OLED模块。它由封装在

玻璃中的OLED单元（116x118mm

）和包含驱动器的

背板组成（图1）。该器件的概念在 [3]中描述。

OLED模块的层结构如图1所示。背板与OLED单元具

有相同的尺寸。OLED单元的阴极覆盖在单元底部，由金

属层M0表示。介质层D0表示OLED单元的玻璃封装以及

OLED单元与背板之间的胶水。背板由250微米厚的FR4

基板（层D1）和两个35微米厚铜层（M1和M2）构成。

电感器制作在金属层M2上。金属层M1面向OLED单元。

图2显示了平面电感器设计及其几何参数。设计参数

包括走线宽度 w、走线间距 s、填充比 R 和外尺寸 D。

填充比 R 是给定几何形状下电感器匝数 N 与最大匝数

max

之比。

平面电感器的尺寸及其电感受到OLED单元尺寸的限

制。由于平面电感器靠近OLED阴极，平面电感器与阴极

之间的接近会导致电感退化

图2.由两个子线圈构成的平面电感器的几何结构及其设计参数，端口P0、P1 和

P2 ，以及带有标记参考平面 ∆‑∆

的端口结构（M1‑浅灰色和M2‑深灰色）。

涡流和增加的寄生电容。平面电感器实现于背板的M2层，

即距离OLED单元较远的一层，以减小OLED与平面电感

器之间的寄生电容。连接电感器、驱动器和OLED单元的

铜导线则实现于金属层M1。该平面电感器由两个对称且

反向绕制的子线圈组成。这两个子线圈将产生方向相反的

磁矩。

平面电感器被定义为双端口结构。端口位于图2中电

感器布局的P1 和P2 处。端口通过通孔连接到金属层M1。

为了建立平面电感器的电气特性与其设计参数之间的

关系模型，对OLED模块进行了3D电磁仿真。使用

COMSOLMultiphysics软件包的RF模块 [16] 来仿真该

电感器结构的S参数。

感兴趣的频率范围为300千赫至300兆赫。下限频率

设定在降压转换器工作频率约一个数量级以下，而上限频

率则设定为包含所分析电感器的谐振行为。

三、等效电路建模

图3显示了本文所考虑系统的电路图，即降压转换器

的输出级、平面电感器和OLED单元。

降压转换器的输出级由开关pDMOS晶体管 T

和续流

二极管 D

组成。该晶体管 T

以其导通电阻

DS,ON为特征，

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while the diode D

is characterized by its forward voltage V

The PWM signal at the frequency f

drives the pDMOS

transistor. A commercial buck converter with the switching

frequency f

= 3.6 MHz is used. The switching transistor

is connected to the power supply voltage V

= 24 V which

is a standard voltage in solid-state lighting applications.

The OLED tile is represented by D

OLED

. Its considerable

capacitance caused by its large-area electrodes is modelled by

OLED

. R

OLED

models the resistance of the indium tin oxide

(ITO) layer [17]. The nominal voltage of the analysed OLED

cell is V

OU T

= 13.7 V and the nominal current is I

OU T

400 mA.

The two-port π-type electrical model consisting of Y

, Y

and Y

represents the planar inductor. The port admittances

and Y

characterize the port capacitances which are critical

because of a small distance between the inductor tracks and the

OLED cathode. Y

describes the admittance of the inductor.

The planar inductor is characterized by its two-port S-

parameters s

ij,m

, while the admittances Y

, Y

and Y

of the

π-model are deﬁned as

= y

11,m

12,m

+ y

21,m

(1)

= y

22,m

12,m

+ y

2,m1

(2)

= −

12,m

+ y

21,m

(3)

where y

ij,m

are the y-parameters obtained from the measured

or simulated S-parameters [18].

The series resistance at the DC frequency is

S,DC

= R

= Re







(4)

where f

is the chosen low frequency (f

= 300 kHz).

The skin depth of the copper tracks at 300 kHz frequency

is approx. 120 µm. Compared to the actual thickness of the

copper tracks of 35 µm, it can be assumed that the skin effect

is not pronounced at this frequency and that the extracted

resistance is approx. equal to the DC resistance of the planar

inductor.

Fig. 3. The models of the buck converter, the planar inductor and the OLED

cell.

Fig. 4. The series resistance and inductance of a typical planar inductor.

The series resistance at the switching frequency and its odd

harmonics is

S,n

= R

S W

= Re







S W

(5)

where f

is the switching frequency and nf

is the n-th

harmonic of the switching frequency.

The series inductance at the operating frequency is

S,AC

= L

S W

= Im







S W

2πf

. (6)

Fig. 4 shows the series resistance and inductance for a

typical inductor design. It shows the extracted series resis-

tances R

S,DC

and R

S,n

and the series inductance L

S,AC

the corresponding frequencies.

The capacitance of the port P1 is extracted using

P 1

= Im [Y

S W

2πf

. (7)

The ﬁrst resonant frequency of the planar inductor is the

lowest frequency at which the condition (8) is satisﬁed.







= 0 (8)

IV. BUCK CONVERTER REQUIREMENTS

The planar inductor in the buck converter topology serves

as an energy storage element. The energy is stored in the

magnetic ﬁeld of the inductor. The parasitic components of

the inductor introduce power losses and consequently reduce

the buck converter efﬁciency.

The efﬁciency of the whole buck conversion process de-

pends on multiple factors among which the quality factor Q

of an inductor is usually deﬁned as

Q(ω) =

Re[Y

(ω)]

Im[Y

(ω)]

ωL

(ω)

(9)

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