################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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温馨提示
这是一个基于AXI4-Lite总线的可配置寄存器IP核,专为FPGA设计中的寄存器配置需求而开发。该IP核具有以下特点: 核心特性: 支持1-8个可配置输出寄存器(写操作) 支持1-8个可配置输入寄存器(读操作) 32位数据宽度,符合AXI4-Lite标准 参数化设计,寄存器数量灵活可调 技术亮点: 智能端口显示,仅显示激活的寄存器接口 完整的AXI VIP仿真测试环境 经过充分验证的功能正确性 应用场景: 反射内存从板配置寄存器 外设控制寄存器映射 状态监控寄存器组 通用配置寄存器模块 资源包含完整的Vivado源码、IP封装文件、测试平台及仿真脚本,开箱即用,可直接集成到您的Vivado工程中。
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AXI4-Lite可配置寄存器IP核(AXI-Reg) - Vivado源码及测试工程 (304个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
simulate.bat 972B
compile.bat 886B
runme.bat 229B
runme.bat 229B
design_1.bd 4KB
design_1.bxml 3KB
xsim_3.c 201KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0.cpp 6KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
design_1_axi_vip_0_0_sc.cpp 4KB
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
axi_vip.cpp 980B
xsim.crvsdump 28KB
xsim.dbg 464KB
design_1_AXI_reg_0_0.dcp 74KB
design_1_AXI_reg_0_0.dcp 74KB
design_1_AXI_reg_0_0.dcp 74KB
design_1_axi_vip_0_0.dcp 20KB
design_1_axi_vip_0_0.dcp 20KB
design_1_axi_vip_0_0.dcp 20KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
simulate.do 377B
simulate.do 371B
simulate.do 371B
elaborate.do 267B
simulate.do 193B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 2.61MB
run.f 2KB
run.f 2KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0.h 4KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
design_1_axi_vip_0_0_sc.h 3KB
axi_vip.h 656B
axi_vip.h 656B
axi_vip.h 656B
axi_vip.h 656B
axi_vip.h 656B
axi_vip.h 656B
axi_vip.h 656B
axi_vip.h 656B
axi_vip.h 656B共 304 条
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